Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
نویسندگان
چکیده
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is presented in this paper. In this work "static" pin mapping and test scheduling for concurrent testing are studied for the case of multiple test sets for each core. The problem is formulated as a constrained two-dimensional bin-packing problem. A heuristic algorithm is then proposed to determine a solution. The objectives driving this solution are geared towards reducing the total test application time of SOC and satisfying the test constraints such as limited number of SOC pins and maximum peak power dissipation specified by core integrators. Experimental results demonstrate the effectiveness of the
منابع مشابه
Optimal Test Time for System-on-Chip Designs using Fuzzy Logic and Process Algebra
Problem statement: Test scheduling is crucially important for optimal SoC test automation to allocate the limited available test resources. In this study we introduced a fuzzy based engine to allocate test resources. The minimized test application time can be achieved by test pipelining. However the test power consumption incurred during test procedure must be controlled in order not to offend ...
متن کاملPower-Time Tradeoff in Test Scheduling for SoCs
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use the power profile of non-embedded cores to find the best mix of their test pattern subsets that satisfy the power and/or time constraints. An MILP formulation is presented to globally perform the power-time tradeoff and...
متن کاملTest Design and Optimization for Multiple Core Systems- On-a-Chip using Genetic Algorithm
Core based design has become the de-facto design style for many VLSI design houses, as it facilitates design reuse, import of specialized expertise from external vendors and leads to a more streamlined design flow. Pre-designed cores and reusable modules are popularly used in the design of large and complex Systems-on-aChip (SOC). Embedded cores such as processors, custom application-specific i...
متن کاملSOC Test Time Minimization Under Multiple Constraints
In this paper, we propose a SOC (system-on-chip) test scheduling technique that minimizes the test application time while considering test power limitations and test conflicts. The test power consumption is important to consider since exceeding the system’s power limit might damage the system. Our technique takes also into account test conflicts that are due to cross-core testing (testing of in...
متن کاملOptimization of Scan Time of Scan Test in System-on-chip
We present an SoC testing approach that integrates test data compression, T AM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as the compression engine. All cores on the SoC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits from the test cube...
متن کامل